AMD says it took four steps to get the new Strix Halo uber APU right, including designing new processor dies that “put Threadripper in your hands.”
AMD’s new Strix Halo Uber APU for laptops was already quite interesting, thanks to its 256-bit memory bus and giant iGPU. It now turns out that its origins were a little unusual: AMD took four tries to get it right, and added some tricks to its processor in the process.
In an interview with the Chips and Cheese website, AMD Senior Research Scientist Mahesh Subramony revealed some new details about the inner workings of the Strix Halo. Subramony says AMD “took four iterations” to get Strix Halo right.
Perhaps this isn’t such a big surprise considering Strix Halo has been rumored for a while now and came out a little later than initial expectations. What’s new is that the Strix Halo’s CCDs may not be quite what you expected.
When the APU was first introduced, it looked like AMD took a couple of its eight-core Zen 5 processor CCDs and squeezed them into a package with a new I/O die containing a huge (for an APU) iGPU with 40 CUs.
Well, that’s not true. Strix Halo has its own CPU CCDs. They’re still based on Zen 5, but AMD has tuned the CCDs to suit the mobile capabilities of the Strix Halo.
First, they have a new gateway. Subramony argues that the existing interconnect that AMD uses between CCDs in its Zen 5 desktop chips like the Ryzen 9 9950X is fast, but has limitations when it comes to power efficiency, including the range of power states supported.
The new interconnect for Strix Halo is said to be better in every way. “Low power, same high throughput, 32 bytes per cycle round trip, lower latency,” explains Subramony. He also says switching power states is now “almost instantaneous.”
Flaw? It’s a little more expensive to make than connecting a desktop computer. However, Subramony also claims that Strix Halo is a full-featured implementation of Zen 5, including a 512-bit FPU.
“I almost joke about it, saying it’s a Threadripper that you can put in the palm of your hand. So we didn’t make any effort. They have a 512-bit data path. It’s a complete desktop architecture,” he says.
The only exception is the clock speed. “We have combined parts to improve efficiency. So they may not reach the same peak frequency that you would see on a desktop computer,” explains Subramony.
He also says that the 32MB of Infinity cache on the GPU die cannot currently be directly accessed by the CPU, it is dedicated to the GPU, although this may change in the future. “We’ll change it up a bit, but right now we don’t see an application where we need to increase CPU throughput,” he says.
More details about the inner workings of Strix Halo are provided in the interview. But suffice it to say that what was already one of the most interesting chips in recent years has become even more intriguing.
The effort AMD has clearly put into the Strix Halo also bodes well for its performance and battery life. If anything, it was the latter that was the most unknown in Strix Halo. Can AMD really cram 16 Zen 5 cores and a huge GPU into a power-efficient package?
I doubted it, of course. But after learning more about the technology AMD has implemented in the Strix Halo, I can’t wait to see how good AMD’s Uber APU really is.